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this is information on a product in full production. september 2012 doc id 11599 rev 4 1/12 12 DVIULC6-4SC6 ultralow capacitance esd protection datasheet ? production data features 4-line esd protection (iec 61000-4-2) protects v bus when applicable ultralow capacitance: 0.6 pf at 825 mhz fast response time compared with varistors sot23-6l package rohs compliant benefits esd standards compliance guaranteed at device level, hence greater immunity at system level esd protection of v bus , when applicable, allows esd current flowing to ground when esd event occurs on data line optimized rise and fall times for maximum data integrity consistent d+ / d- signal balance: ? optimum capacitance matching tolerance for ultralow intra-pair skew: i/o to ground = 0.015 pf, i/o to i/o = 0.007 pf ? matching high bit rate dvi, hdmi, and ieee 1394 requirements low pcb space occupation: 9 mm 2 low leakage current for longer operation of battery powered devices higher reliability offered by monolithic integration complies with these standards iec 61000-4-2 level 4: ? 15 kv (air discharge) ? 8 kv (contact discharge) mil std883g-method 3015-7 applications dvi ports up to 1.65 gb/s hdmi ports up to 1.65 gb/s ieee 1394a, and b up to 1.6 gb/s usb 2.0 ports up to 480 mb/s (high speed), backwards compatible with usb 1.1 low and full speed ethernet port: 10/100/1000 mb/s sim card protection video line protection description the DVIULC6-4SC6 is a monolithic, application specific discrete device dedicated to esd protection of high speed interfaces, such as dvi, hdmi, ieee 1394a, and b, usb 2.0, ethernet links and video lines. its ultralow line capacitance secures a high level of signal integrity wit hout compromise in protecting sensitive chips against the most stringently characterized esd strikes. sot23-6l (jedec mo178ab) www.st.com
characteristics DVIULC6-4SC6 2/12 doc id 11599 rev 4 1 characteristics figure 1. functional diagram table 1. absolute ratings symbol parameter value unit v pp peak pulse voltage iec 61000-4-2 air discharge iec 61000-4-2 contact discharge mil std883g-method 3015-7 15 15 25 kv p pp peak pulse power 80 w t stg storage temperature range -55 to +150 c t j operating junction temperature range -40 to +125 c t l lead solder temperature (10 seconds duration) 260 c table 2. electrical characteristics (t amb = 25 c) symbol parameter test conditions value unit min. typ. max. i rm leakage current v rm = 5 v - - 0.5 a v br breakdown voltage between v bus and gnd i r = 1 ma 6 - - v v cl clamping voltage i pp = 1 a, t p = 8/20 s any i/o pin to gnd --12v i pp = 5 a, t p = 8/20 s any i/o pin to gnd --17v c i/o-gnd capacitance between i/o and gnd v r = 0 v, f= 1 mhz - 0.85 1 pf v r = 0 v, f= 825 mhz - 0.6 - ? c i/o- gnd capacitance variation between i/o and gnd --0.015- c i/o-i/o capacitance between i/o v r = 0 v, f= 1 mhz - 0.42 0.5 pf v r = 0 v, f= 825 mhz - 0.3 - ? c i/o-i/o capacitance variation between i/o --0.007- 1 1 6 2 5 3 4 i/o1 i/o4 gnd v bus i/o2 i/o3
DVIULC6-4SC6 characteristics doc id 11599 rev 4 3/12 figure 2. line capacitance versus line voltage (typical values) figure 3. line capacitance versus frequency (typical values) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f=825mhz v osc = 500mv rms v bus open t j =25 c 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 data line voltage (v) c i/o - gnd c(pf) 0 v osc =30mv rms t j =25 c v i-o/gnd = 0v f(mhz) 1 10 100 1000 10000 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 c(pf) c i/o - gnd c i/o -c i/o v open bus figure 4. relative variation of leakage current versus junction temperature (typical values) figure 5. frequency response 1 2 3 4 5 25 50 75 100 125 i[t rm j ] / i [t rm j =25c] t (c) j 100.0k 1.0m 10.0m 100.0m 1.0g 100.0k 1.0m 10.0m 100.0m 1.0g 100.0k 1.0m 10.0m 100.0m 1.0g 0 -2 -4 -6 -8 f(hz) s21(db) attenuation figure 6. remaining voltage after the DVIULC6-4SC6 during positive esd surge (1) figure 7. remaining voltage after the DVIULC6-4SC6 during negative esd surge (1) 1. measurements were done with dviulc-4sc6 in open circuit
characteristics DVIULC6-4SC6 4/12 doc id 11599 rev 4 figure 8. analog crosstalk results 100.0k 1.0m 10.0m 100.0m 1.0g - 120.00 - 90.00 - 60.00 - 30.00 0.00 db f (hz)
DVIULC6-4SC6 application examples doc id 11599 rev 4 5/12 2 application examples figure 9. dvi/hdmi digital single link application figure 10. t1/e1/ethernet protection 1 1 6 2 5 3 4 1 1 6 2 5 3 4 1 1 6 2 5 3 4 1 1 6 2 5 3 4 de de pixel data pixel data clock clock vsync vsync hsync hsync graphics controller tmds transmitter tmds receiver display controller host (pc, graphics cards, set-top box, dvd player) display (lcd monitor, flat panel,display, projector) rx0- tx0- rx0+ tx0+ rx1- rx1+ rx2- rx2+ tx1- tx1+ tx2- tx2+ rc- tc- rc+ tc+ tmds links dvi connector +v cc 100nf data transceiver smp75-8 smp75-8 tx rx 1 1 6 2 5 3 4
technical information DVIULC6-4SC6 6/12 doc id 11599 rev 4 3 technical information 3.1 surge protection the DVIULC6-4SC6 is particularly optimized to perform esd surge protection based on the rail to rail topology. the clamping voltage v cl can be calculated as follows: v cl + = v bus + v f, for positive surges v cl - = - v f, for negative surges with: v f = v t + r d .i p v f = forward drop voltage, v t = forward drop threshold voltage) calculation example we can assume that the value of the dynamic resistance of the clamping diode is typically: r d = 1.4 ? and v t = 1.2 v. for an iec 61000-4-2 surge level 4 (contact discharge: v g = 8 kv, r g = 330 ? ), v bus = +5 v, and, in a first approximation, we assume that: i p = v g / r g = 24 a. we find: v cl + = +39 v v cl - = -34 v note: the calculations do not take into account phenomena due to parasitic inductances. 3.2 surge protection application example if we consider that the connections from the pin v bus to v cc and from gnd to pcb gnd plane are two tracks 10 mm long and 0.5 mm wide, we can assume that the parasitic inductances, l w of these tracks are about 6 nh. so when an iec 61000-4-2 surge occurs, due to the rise time of this spike (tr = 1 ns), the voltage v cl has an extra value equal to l w di/dt. the di/dt is calculated as: di/dt = i p /t r = 24 a/ns for an iec 61000-4-2 surge level 4 (contact discharge v g = 8 kv, r g = 330 ?? the over voltage due to the parasitic inductances is: l w .di/dt = 6 x 24 = 144 v by taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be: v cl + = +39 + 144 = 183 v v cl - = -34 - 144 = -178 v we can reduce as much as possible these phenomena with simple layout optimization. this is the reason why some recommendations have to be followed (see section 3.3: how to ensure good esd protection ).
DVIULC6-4SC6 technical information doc id 11599 rev 4 7/12 3.3 how to ensure good esd protection while the DVIULC6-4SC6 provides a high immunity to esd surge, an efficient protection depends on the layout of the board. in the same way, with the rail to rail topology, the track from v bus pin to the power supply +v cc , and from v bus pin to gnd pin must be as short as possible to avoid over voltages due to parasitic phenomena (see figure 11 and figure 12 for layout considerations). figure 11. iesd behavior: parasitic phenomena due to unsuitable layout figure 12. esd behavior: layout optimization and addition of a 100 nf capacitor lw vi/o esd surge gnd i/o +v cc v bus v f lw di dt lw di dt v+ = cl v +v +lw bus f di dt surge >0 di dt surge <0 v- = cl -v -lw f t tr=1ns vv cc f + lw di dt v cl + positive surge 183v -lw di dt t tr=1ns - v f v cl - negative surge -178v ref1=gnd vi/o esd surge i/o ref2=+ v cc c=100nf lw v+ v cl cc f v+ = surge >0 surge <0 vv cl f - - = t v+ cl positive surge t v- cl negative surge
technical information DVIULC6-4SC6 8/12 doc id 11599 rev 4 figure 13. pcb layout considerations (v cc connection is application dependent) it?s often harder to connect the power supply near to the DVIULC6-4SC6 unlike the ground thanks to the ground plane that allows a short connection. to ensure the same efficiency for positive surges when the connections can?t be short enough, we recommend putting close to the DVIULC6-4SC6, between v bus and ground, a capacitance of 100 nf to prevent these kinds of disturbances (see figure 12 and figure 13 ). the addition of this ca pacitance will allow a better protection by providing a constant voltage during a surge. figure 14 , figure 6 , and figure 7 show the improvement of the esd protection according to the recommendations described in section 3.3 . figure 14. esd behavior: measurement conditions (with coupling capacitor) important: an important precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector). d+1 c = 100nf d-1 gnd DVIULC6-4SC6 d+2 d-2 v cc 1 dvi connector side v cc (+5v) c=100 nf esd surge test board DVIULC6-4SC6h
DVIULC6-4SC6 technical information doc id 11599 rev 4 9/12 3.4 crosstalk behavior figure 15. crosstalk phenomena the crosstalk phenomena is due to the coupling between 2 lines. the coupling factor ( ? 12 or ? 21 ) increases when the gap acro ss lines decreases, particularly in silicon dice. in the example above the expected signal on load r l2 is ? 2 v g2 , in fact the real voltage at this point has got an extra value ? 21 v g1 . this part of the v g1 signal represents the effect of the crosstalk phenomenon of line 1 on line 2. this phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. the perturbed line will be more affected if it works with low voltage signal or high load impedance (few k ? ). figure 16. analog crosstalk measurements figure 16 gives the measurement circuit for the anal og application. in usual frequency range of analog signals (up to 240 mhz) the effect on disturbed line is less than -45 db (see figure 8 ). as the DVIULC6-4SC6 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. the frequency response ( figure 5 ) gives attenuation information and shows that the DVIULC6-4SC6 is well suitable for data line transmission up to 1.65 gb/s. line 1 line 2 v g1 v g2 r g1 r g2 drivers r l1 r l2 receivers + 1 12 v g1 v g2 + 2 21 v g2 v g1 spectrum analyser 50 w tracking generator vg 50 w test board c=100nf spectrum analyser v out 50 tracking generator v g v in 50 test board v cc c=100nf dviulc6
package information DVIULC6-4SC6 10/12 doc id 11599 rev 4 4 package information epoxy meets ul94, v0 lead-free packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 17. footprint - dimensions in mm [inches] table 3. sot23-6l dimensions ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.90 - 1.45 0.035 - 0.057 a1 0 - 0.15 0 - 0.006 a2 0.90 - 1.30 0.035 - 0.051 b 0.30 - 0.50 0.012 - 0.020 c 0.09 - 0.20 0.004 - 0.008 d 2.80 - 3.05 0.11 - 0.118 e 1.50 - 1.75 0.059 - 0.069 e - 0.95 - - 0.037 - h 2.60 - 3.00 0.102 - 0.118 l 0.30 - 0.60 0.012 - 0.024 ? 0 - 10 0 - 10 a2 a l h c b e d e e a1 q 0.95 [0.037] 0.60 [0.023] 1.20 [0.047] 1.10 [0.043] 3.50 [0.138] 2.30 [0.091]
DVIULC6-4SC6 ordering information doc id 11599 rev 4 11/12 5 ordering information 6 revision history table 4. ordering information order code marking package weight base qty delivery mode DVIULC6-4SC6 dl46 sot23-6l 16.7 mg 3000 tape and reel table 5. document revision history date revision changes aug-2005 1 first issue. 09-apr-2010 2 ecopack statement updated. operating junction temperature range specified in ta b l e 1 . 14-sep-2011 3 added peak pulse power in ta bl e 1 . 06-sep-2012 4 updated illustration and dimensions a1 max., b min., and l min. in ta bl e 3 .
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